1. Field of the Invention
This invention relates to semiconductor memory devices having a page mode reading function.
2. Description of the Background Art
In semiconductor memory devices such as DRAMs in which memory cells per se have no logic outputting function of “H” and “L” levels, a sense amplifying operation is required in order to detect and amplify data stored in the memory cells and convert the data into logical value (“H” and “L”). As performing the sense amplifying operation on a word-by-word basis will extremely delay access to data, a page mode reading function is widely used in which data recorded in a plurality of words of memory cells are simultaneously read (including the sense amplifying operation) and temporarily stored in a latch, so that the data are accessible with read time from the latch the second and subsequent times. Semiconductor memory devices having the page mode reading function are disclosed, for example, in Japanese Patent Application Laid-Open Nos. 7-73664 (1995) and 11-39863 (1999).
When a semiconductor memory device having the page mode reading function includes 16 data output pins (of 16 bits) in response to an access request from an LSI capable of processing 16 bytes (128 bits (1 byte=8 bits)) of data at a time, for example, a page mode function of 8 words (128 bits (in terms of 1 word =16 bits)), that is, a page mode function of 8 words of page length, would allow 128 bits of data to be read by a onetime sense amplifying operation, thus achieving high-speed data transmission with the LSI. Electronic equipment that employs a semiconductor memory device having the page mode reading function includes mobile phone, for example.
However, a word length increase of page mode involves an increase in the number of simultaneously activated sense amplifiers and also an increase in memory capacity of a latch for temporarily storing data, resulting in problems such as an increase in peak current value and an increase in layout area of a transistor or wiring.